LICENSED TECHNOLOGY IMPSPRGM™ is proprietary technology of LLC IMPSPRGM · supplied under a written Licence Agreement on a per-unit basis.
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IMPSPRGM · Interprocessor OTA

One signed bundle updates both cores of a dual-chip node over a single GSM link. Reference design: SIM800C (SIMCom) + STM8 (STMicroelectronics) — no external programmer, no field visit.

Licensed technology · built on the IMPSPRGM three-bus runtime · international PCT application PCT/UZ2022/050001

This page builds on IMPSPRGM · Interprocessor OS →. The three logical buses and the Translator described there are the transport for everything below.

The problem — updating two chips in the field

A dual-chip telemetry node has two firmware images that must always agree: the radio-side application running inside the modem, and the real-time logic on the MCU. In a conventional design each is updated by its own path — the modem app through the vendor's flash tooling, the MCU through a wired programmer on a service bench. That means a technician has to physically reach a device that may be inside a wall, a pit or a sealed enclosure; the two images can drift out of step; and a half-finished write on an 8-bit MCU with no second bank can brick the unit permanently.

Interprocessor OTA removes the programmer and the site visit. A single signed bundle arrives over the air, and the two cores update themselves in a coordinated, reversible sequence — using resources that are already on the board.

One bundle, two cores

The modem is the only part of the node with a wide-area link, megabytes of flash and a TCP stack, so it acts as the update host. The MCU is the update target that cannot reach the network on its own. IMPSPRGM lets the host flash the target across the same three-bus link used at runtime.

Architecture at a glance

IMPSPRGM Interprocessor OTA — modem as update host flashing the STM8 target over the shared bus
Fig. 1 · The modem hosts the download and drives the update; the MCU is flashed across the same three logical buses used during normal operation.

Because the update rides the existing buses, no extra pins, no debug header and no second radio are required. The MCU is written through its own on-chip mechanisms — the built-in UART bootloader for a full re-flash, or in-application programming (IAP) for a running update — both driven remotely by the modem.

Bus 1 · Commands — control the update

Short opcodes move the target between states: OTA_BEGIN, ENTER_BOOTLOADER, ERASE_PAGE(n), OTA_COMMIT, OTA_ABORT. Each side serves only the opcodes it can, so the same sequence works whether the MCU is updated via its bootloader or via IAP.

Bus 2 · Procedures — move and verify the image

The bulk of the work is a stream of remote procedure calls: write_page(addr, bytes) → ack and read_crc(addr, len) → crc16. Every page written to the target is read back and checksummed over the same call, so a corrupted transfer is caught immediately and re-sent, not discovered after reboot.

Bus 3 · Interrupts — progress and abort

Asynchronous tokens report progress (page k/N done), power events (a brown-out during flashing), and operator aborts. A low-battery interrupt can pause an update before an unsafe write and resume it after the next uplink.

Update sequence

Sequence diagram — modem downloads a signed bundle, verifies it, then flashes the STM8 page by page and commits atomically
Fig. 2 · Download → verify → page-by-page flash with read-back → atomic commit. A failed health check on either core triggers a coordinated rollback.
  1. Server publishes a new bundle; the node learns of it on its next scheduled uplink (or via an SMS wake).
  2. Modem downloads the bundle into EAT flash over the open socket, resuming across dropped connections.
  3. Signature verified on the modem; the delta for each core is unpacked.
  4. Modem sends OTA_BEGIN, then streams write_page / read_crc pairs to the MCU while staging its own image.
  5. Both cores arm the new images and OTA_COMMIT at one point; a post-boot health handshake confirms success — otherwise both revert.

Atomic by construction

The old images are never erased until the new ones have booted and answered a health handshake across the bus. An interrupted download, a bad page, or a core that fails to check in all resolve to the same safe outcome: the node keeps running the last known-good firmware and reports the failure on its next uplink. There is no state in which one core is new and the other is old.

Security of the update path

Data & power cost

Only the changed regions travel: the bundle carries per-core deltas, not whole images, which keeps a routine update within a handful of kilobytes on the cellular link. The transfer reuses the socket that is already open for telemetry, and the MCU is only woken for the short windows in which it is actually being written — consistent with the anti-phase power strategy of the Interprocessor OS.

What Interprocessor OTA changes for a deployed fleet

0field visits per update
0external programmers on the BOM
1signed bundle, both cores
2cores updated in lock-step
A / Bknown-good rollback

Where Interprocessor OTA fits

References

Licensing & Intellectual Property

Commercial licensing model

IMPSPRGM™ is proprietary technology of LLC IMPSPRGM (Tashkent, Republic of Uzbekistan). The technology — including the reference firmware, the translator mechanism, the three-bus protocol, the over-the-air update path, the hardware integration library and the supporting design files — is distributed exclusively under a written Licence Agreement between LLC IMPSPRGM and the Licensee.

The licence is granted on a per-unit (per-device) basis. The Licence Agreement specifies the exact number of end devices in which IMPSPRGM may be embedded, and any additional units above that number require either a licence extension or a new agreement.

Commercial inquiries and per-unit quotations: impsprgm@umail.uz

Copyright & PCT protection

The IMPSPRGM technology is protected under the international Patent Cooperation Treaty (PCT). The application was filed electronically via ePCT-Filing and acknowledged by the Receiving Office.

Submission Number050001
Application NumberPCT/UZ2022/050001
Date of Receipt29 December 2022
Receiving OfficeIntellectual Property Agency under the Ministry of Justice of the Republic of Uzbekistan (RO/UZ)

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